A power switching converter is based on switching controllable switches, which apply a chopped voltage to a filtering circuit made up of inductive and capacitive components. Controlling the opening and closing moments of the or each switch makes it possible, through interaction with the charge connected at the output of the converter, to generate a greater or smaller voltage and/or current at the output of the converter.
FIG. 1 for example shows a passive rectification non-inverter converter 10 according to a “Buck-Boost” topology.
The known converter has two controllable switches S1 and S2 (preferably MOSFET switches); two passive rectifiers R1 and R2 (preferably diodes); an inductive L switching component (preferably an inductance).
It is by varying the duty ratio of the command signal SC1 of the transistor S1 and that of the command signal SC2 of the transistor S2 that the current IL in the inductance L is adjusted and, consequently, the output voltage Vout across the output terminals 13 and 14.
The fact that the rectification is passive, i.e. done by diodes and not transistors, makes the converter unidirectional, preventing negative currents in the inductance L and making it possible to operate in intermittent flow.
The operating phases of the converter 10 for a continuous flow, i.e., for a large enough charge connected to the output, such that the current IL through the inductance L is not canceled out, are shown as a function of time t in FIGS. 2 and 4 for the voltage VL across the terminals of the inductance L and in FIGS. 3 and 5 for the current IL through the inductance L.                “Boost” phase: between moments t1 and t2, the transistors S1 and S2 are both commanded to close. The input voltage Vin, across the terminals 11 and 12, is therefore applied to the inductance L. The voltage VL being positive, the current IL increases.        “Buck” phase: between moments t2 and t3, the switch S2 then being commanded to open, the rectifier R2 becomes on. It is the difference between the input voltage Vin and output voltage Vout that is applied to the inductance L. As a function of the difference between these voltages, the voltage applied to the inductance will be positive (FIG. 2) or negative (FIG. 4). The current IL will therefore increase (FIG. 3) or decrease (FIG. 5).        “Free-wheeling” phase: between moments t3 and t4, the two switches S1 and S2 are commanded to open. The rectifiers R1 and R2 are then both on. The output voltage Vout is then applied in reverse on the inductance L. The current IL then decreases.        
Considering that the state is steady, the current at the beginning of the “Buck” phase is equal to the current at the end of the “free-wheeling” phase and the phases follow one another periodically.
The converter 10 includes a control device 20 making it possible to determine the moment at which to command the closing and the moment at which to command the opening of the transistors S1 and S2, and to generate the command signals SC1 and SC2 to be applied to the transistors S1 and S2, respectively.
Hereinafter, it is considered that the converter is controlled continuously using the principle described in patent EP 2,432,108 A1. Thus, the switch S2 is commanded by the control device 20 continuously as a function of the input voltage Vin, while the switch S1 is controlled by the control device 20 continuously as a function of the output voltage Vout. The switches S1 and S2 therefore work at duty ratios different from zero and one. In other words, they operate continuously in switching, irrespective of the ratio of the input and output voltages, whether the converter raises or lowers the voltage. Hereinafter, we more particularly examine the switch S1 and the development of the command signal SC1.
To command the first switch S1, the control device 20 includes an error corrector 22 on the output voltage Vout relative to a reference voltage Vcons. The output signal of the error corrector does not directly control the transistor S1, but constitutes a reference signal Scons for a current control loop.
The current control loop making it possible to slave the current circulating in the transistor S1 on the reference signal Scons can in particular be done using a “peak current” control mode or a “peak charge” control mode (also called “integrated current”). These two principles are illustrated in the same FIG. 6.
According to the “peak current” mode, the control device 20 of the converter makes it possible to slave the peak value of the current in the transistor S1 and the inductance L on the reference signal Scons. The opening of the transistor S1 is then triggered by a comparator 24, at the end of the comparison of a measurement of the current Imes circuiting in the transistor S1 with the reference signal Scons. The measurement of the current Imes is done by a current sensor 25 and applied on one of the input tabs of the comparator 24 (dotted lines in FIG. 6). The output signal of the comparator 24 is applied on the reversed reset input of a latch 28 controlled by a clock signal CLK, which makes it possible to place the output Q of the latch 28 in the high state “1” at each pulse edge of the clock signal CLK. The output Q is then switched into the low state “0” when the output signal of the comparator 24 is in the low state “0”. The output signal of the latch 28 constitutes the command signal SC1 of the transistor S1.
According to the “peak charge” mode, the control device 20 of the converter makes it possible to slave the peak value of the charge in the transistor S1 and the inductance L on the reference signal Scons. The opening of the transistor S1 is then triggered by a comparator 24, at the end of the comparison of a measurement of the charge Qmes circuiting in the transistor S1 with the reference signal Scons. The measurement of the charge Qmes is obtained by a time integrator 26 of the measurement of the current Imes delivered by the sensor 25. The time integrator 26 is reset to zero upon each switching period, by the clock signal CLK, which also paces the switching by the latch 28. The measurement of the charge Qmes is applied on one of the input tabs of the comparator 24 (solid lines in FIG. 6). The output signal of the comparator 24 is applied on the reversed reset input of the latch 28 controlled by a clock signal CLK, which makes it possible to place the output Q of the latch 28 in the high state “1” at each pulse edge of the clock signal CLK. The output Q is then switched into the low state “0” when the output signal of the comparator 24 is in the low state “0”. The output signal of the latch 28 again constitutes the command signal SC1 of the transistor S1.
The implementation of a control in “peak current” mode for controlling the converter 10 is, however, problematic for an input voltage Vin lower than the output voltage Vout. Indeed, the current IL being decreasing in the “Buck” phase that precedes the opening of the switch S1, control in “peak current” mode cannot be done directly. It is in fact necessary to add a compensating ramp. Control in “peak current” mode with a low input voltage is then comparable to a control in “voltage” mode, in which the compensating ramp is predominant relative to the ramp of the measured current.
Furthermore, independently of the topology of the controlled converter, control in “peak current” mode has a certain number of drawbacks:
i) Imprecision of the current or power limitation: in the majority of cases, the “peak current” mode is used to produce a limitation of the current or power by limiting the reference signal. But the measurement of the current Imes is not representative of the mean input current (and therefore the input power) or the mean output current (and therefore the output power). Indeed, if we take the example of a converter with a “Buck” topology, for a same peak current, the value of the mean current depends on the amplitude of the current waviness, i.e., input and output voltage values;
ii) Negative input impedance: a switching converter is always accompanied by input filtering, especially when it is connected to an input network. Indeed, the equipment using this converter is subject to standardized EMC constraints, which are reflected by frequency templates of the input current. To respect these frequency templates, one or several LC-type passive filters are added upstream from the input capacitor of the converter for maximal smoothing of the input current and decreasing the chopped current harmonics so as to respect the frequency template.
The Middlebrook criterion then makes it possible to ensure, simply, the stability of the assembly made up of the filter and the converter: the output impedance of the filter must be lower than the input impedance of the converter.
However, for a converter controlled in “peak current” mode, the converter has a negative impedance at low frequency. Indeed, for the same reference signal limiting the peak current, when the input voltage decreases, the mean input current increases.
This may then raise compatibility problems with the filter and requires significant damping of the filter, in order for the resonance thereof not to cause an output impedance of the filter greater than the input impedance of the converter.
This damping is generally bulky, whether in terms of capacitors (it takes a damping capacitor volume at least equivalent to that of the filter to be damped) or resistances (the resistances must be able to withstand the normative susceptibility tests, in particular when the filter is excited at its resonance frequency).
iii) Compatibility with an impedance input network (resistive and/or inductive): the generalization of the composite structures of aircrafts goes hand-in-hand with increasing the impedance of the distribution cabling of electrical grids. Indeed, the fuselage of the aircraft no longer being conducting, it is no longer possible to have the current returns pass through and thus requires the use of return conductors. These conductors are more resistive than the structure, since they offer fewer sections. As a comparison, the cabling impedance (outgoing and incoming) between an aircraft with a metal structure and an aircraft with a carbon structure increases by 67%.
A high line impedance does not work well with a negative input impedance. Indeed, the more the current requested by the converter increases, the greater the voltage drop between the source and the converter is, therefore the converter will demand more current to continue operating at a constant power. This running away is primarily bothersome when starting up the converter, being able to cause stopping/restarting phenomena.
Control in “peak charge” mode makes it possible to avoid these problems associated with control in “peak current” mode. This is why control in “peak charge” mode is largely implemented in the state of the art.
This is primarily due to the fact that the regulation is done not directly on the value of the current in the switch S1, but on the value integrated over time of this current, from the closing of the switch S1 (the integration being reset upon opening of the switch S1, so as to restart at zero at the beginning of each cycle), and that the converter is unidirectional, such that its charge can only increase and such that a control can be done even when the current is not increasing.
Control in “peak charge” mode thus responds to the drawbacks of control in “peak current” mode listed above.
Electrically, the integrated current is homogeneous at a charge. For the example of a “Buck-Boost” converter, this charge, once averaged over a period, is equal to the mean current applied at the input of the converter. One thus directly controls the mean input current of the converter, independently of the waviness of the current in the inductance, i.e., voltages and duty ratios involved. It is therefore possible to have a very precise limitation of the input current.
When considering the reference signal Scons as fixed, the “Buck-Boost” converter behaves like a constant-current charge up to a certain threshold frequency. Approaching this threshold frequency, depending on the switching frequency, but also the control circuits, the input impedance of the converter decreases slightly, before increasing. Thus, while for the “peak current” control mode, the initial slope of the input impedance decreases, which requires damping of the resonance of the upstream filtering to respect the Middlebrook criterion, for the “peak charge” control mode, the initial slope of the impedance being zero, it is easier to respect the Middlebrook stability criterion. It is then possible to reduce the damping of the filtering upstream from the input of the converter, with the advantage of physically reducing its size.
Lastly, in “peak charge” mode, the converter has a real current limitation, and not a power limitation like with the “peak current” mode. The Pin-Vin limit characteristic of the converter can go through the 0-0 point. It should be noted that the Pin-Vin limit characteristic is bounded by a power limitation, supplanting the current limitation for high input voltages. Due to this characteristic, it is possible to have a balance between the impedance of the grid and the input impedance of the converter.
However, control in the “peak charge” mode also has drawbacks. The benefits for the input impedance of the converter and therefore the input filter placed upstream from the latter are only valid for a fixed reference signal Scons. In reality, to regulate the output voltage Vout of the converter, the reference signal Scons is not fixed, but derived from the error corrector 22 between the output voltage Vout and the reference voltage Vcons.
This direct slaving on the output voltage Vout of the reference signal Scons, corresponding to a reference peak charge, raises the following problems:                The slaved property being the reference peak charge, i.e. ultimately the input current of the converter, a power limitation of the converter cannot be done directly. The positive saturation of the error corrector corresponds to a current limitation, but not a power limitation. It is therefore necessary to implement an additional circuit to perform the power limitation function;        as previously stated, in order for the converter to be comparable to a constant-current charge and to obtain the advantages thereof for dimensioning of the upstream filter, the reference peak charge must be constant (or at the very least have a very low frequency). This means that the error corrector must have a very low cutoff frequency. This low cutoff frequency is not compatible with high-voltage spikes that may occur at the input of the converter. As an example, the abnormal surge voltage defined in avionics standard DO-160G is a spike of 28 V to 84 V with a pulse edge below 1 ms. Likewise, the currents induced by lightning strikes create rapid voltage pulse edges. If the input voltage increases while the reference peak charge (i.e., the input current) remains constant, then the converter will allow more power to pass, leading to an overvoltage at the output.        